Results are presented from the Radiation Hardened Electronic Memory Experiment (RHEME-2) performed on the STPSat-5 mission in a polar orbit.

Results are presented from the Radiation Hardened Electronic Memory Experiment (RHEME) performed on the International Space Station (ISS).

Abstract In recent years there has been an increasing selection of commercially available electronic components specified for very high temperature (200C+) operation, driven by the needs of harsh-environment applications such as oil and gas exploration/production, aerospace, heavy industrial, and automotive. However, there remains a significant technical challenge to integrate these components into reliable, high performance systems. We previously presented a complete reference design of a precision multichannel sensor data acquisition and control system rated to 200C, including characterized hardware, firmware, and software. The design is based around low power 16 bit SAR ADCs and an ARM® Cortex®-M0 processor and is optimized for high resolution and high throughput measurements while maintaining low power and a small footprint. In this paper we present the test results of this system over temperature. The reference platform is available off the shelf, including hardware design files, processor firmware source code, and PC software for data logging and display, providing engineers a rapid development tool for prototyping and a faster path to production for complex harsh-environment applications.

Abstract This paper will describe the development and testing of a new ARM© Cortex©-M based microcontroller for high temperature electronic systems. High temperature and electrical overstresses can cause latch-up in CMOS devices that will interfere with normal device operation or destroy the device. For reliable operation in the downhole drilling environment it was necessary to immunize this device against latch-up using an innovation processing technique. HARDSIL® technology that allows reliable latch-up free operation at extreme temperatures will be described. Details on the qualification and testing of the product to ensure that it meets the challenging environment will also be discussed. This includes electrical testing and temperature cycling testing to ensure that the different package options for the silicon device are mechanically sound in a high temperature environment that exposes the silicon and packaging materials to thermal cycling. The ecosystem for the microcontroller will also be discussed – hardware and software development tools are required to optimize the use of the device in extreme temperature embedded systems. An ecosystem of components is also required to operate with the microcontroller in the high temperature harsh environment.

Abstract This paper will describe the development and testing of a new ARM® Cortex®-M based microcontroller for high temperature downhole electronic systems. The trade-offs in the selection of each on-chip peripheral will be discussed with respect to their requirement in the application. Particular detail will be afforded to the underlying high-temperature implementation technology that allows reliable operation at extreme temperatures. High temperature and electrical overstresses can cause latch-up in CMOS devices that will interfere with normal device operation or destroy the device. For reliable operation in the downhole drilling environment it was necessary to immunize this device against latch-up using an innovative processing technique. Details on the qualification and testing of the product to ensure that it meets the challenging environment will also be discussed. This includes electrical testing and temperature cycling testing to ensure that the different package options for the silicon device are mechanically sound in a high temperature environment that exposes the silicon and packaging materials to thermal cycling. The ecosystem for the microcontroller will also be discussed – hardware and software development tools are required to optimize the use of the device in a downhole drilling embedded system. A set of companion components is also required to operate with the microcontroller in the high temperature harsh environment. The components that were selected for use on the high temperature test boards will also be discussed.

In view of the necessity of activity analysis on Gbps-scale 3D Tele-Immersive (3DTI) content bundle and petabyte-scale 3DTI recordings, this work proposes and verifies the feasibility of replacing high-latency intrusive analysis with light-weighted metadata-based analysis. For real-time in-session use case, result shows that metadata-based analysis module, when personalized with user's body index, can achieve accuracies in 90 percentile on classifying various activity classes. For offline cross-session use case, we propose a hybrid analysis scheme which combines the advantages of intrusive analysis (i.e., conventional activity analysis on content level) and metadata-based analysis and achieves high accuracy with low computation latency.

Abstract VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.

Silicon Space Technology has developed a commercial bulk CMOS process technology, HardSIL™, which allows optimization of performance, power, and lifetime at high temperatures. A method for preventing latchup, originally developed for use in the space radiation environment, is presently applied to terrestrial high-temperature environments. With the possibility of latchup eliminated in scaled CMOS technology nodes, further designs specific for high-temperature environments have proceeded well. This novel technology has been applied to our 18Mb synchronous burst SBRAM and our ARM® Cortex® M0 microcontroller, and in two CMOS processes at the 130nm technology node (Texas Instruments and GLOBALFOUNDRIES). Extensive temperature testing on these parts demonstrates that bulk silicon CMOS technology has a practical temperature limit of 250°C or higher. Both the microcontroller and the SBRAM have been tested with clock rates up to 70MHz and at temperatures up to 260°C. Both parts have performed without error and without latchup under these conditions, and with low operating current and low leakage current. For example, the 130 million-transistor 18Mb SBRAM has average core leakage current of 580mA at 250°C and core voltage of 1.5V with test lots and simulations showing further reduction in leakage in the next, terrestrial version of this part. In addition, the 18Mb SBRAM is undergoing an endurance test at 250°C, presently at the 2500 hour milestone. Operation at temperatures beyond the present limit of the testing equipment (260°C) appears possible from extrapolation of current data. Integration levels of greater than 8 million gates on a bulk CMOS device would allow multi-core processors with large on-chip secondary caches. Additional DSP engines or other compute engines can be accommodated for processing high resolution three dimensional images in real time. This would provide substantial distributed processing in drilling or jet engine control. These system-on-chip (SOC) integration levels can substantially reduce mechanical failures in a subsystem by reducing the number of wire bonds from greater than 1000 connections to less than 100 connections. Integration of mixed-signal A/Ds and D/As as well as on-chip power management provides a path to further reduction in mechanical connections in a sub-system.

High density, low power 180nm and 130nm CMOS SRAMs have been manufactured on bulk silicon wafers using a modified CMOS commercial process that hardens the junction isolation and has demonstrated latchup immunity at temperatures >200°C. TCAD simulations confirmed by high temperature testing indicate that a latch up free performance of SRAMs manufactured on bulk silicon modified by the HardSIL™ technology will easily extrapolate to 250°C. These process modifications result in significantly more robust CMOS circuits making them more suitable for highly reliable operations in extreme environments – such as radiation and high temperature. The unique capability of HardSIL™ technology to enhance existing IC products has demonstrated excellent results with several commercial circuits. This new approach enables the conversion of commercial off the shelf (COTS) circuits to hardened hi-rel commercial circuits with dramatically improved survivability to either radiation or high temperatures. Latchup immunity has been demonstrated on two high-density bulk silicon CMOS SRAMs: a 16Mbit asynchronous SRAM manufactured at the 180nm design node and an 8Mbit dual port synchronous SRAM manufactured at 130nm. Both parts were produced in a high-volume, low-defect commercial CMOS fabrication facility in the USA. The SRAM parts were packaged in ceramic packages and characterized at temperatures ranging from 25°C to 225°C. Characterization data indicates both excellent static leakage and dynamic circuit performance for both SRAMs at these elevated temperatures. Device test structures designed with typical layout spacing rules were evaluated to quantify latchup and isolate the various leakage mechanisms. Detailed results for these test structures are presented and compared to the SRAMs using the modified HardSIL™ process.