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Abstract
Polarization independent silicon-on-insulator nanowires are highly sought after, due the inherent high birefringence of this material platform. State-of-the-art designs of non-birefringent waveguides include ridge waveguides and square nanowires, which either imply large dimensions, multiple etching steps, low fabrication tolerances or high wavelength dependence. In this work, we overcome all the aforementioned limitations through tilted subwavelength structures which provide anisotropy control of the resulting metamaterial. With a waveguide cross section of only 300 nm x 550 nm (height x width), the zero-birefringence point is obtained for an approximately 48°-tilt of the subwavelength structure. Birefringence of the nominal design deteriorates by only 9.10 -3 even in the presence of size deviations of +10 nm. Moreover, birefringence is maintained under 6.10 -3 in a 100-nm bandwidth around the central wavelength of 1550 nm. This innovative approach is readly adaptable to a wide range of waveguide sizes, while maintaining single-etch-step fabrication.
Highlights
Silicon-on-insulator (SOI) photonic platforms have experienced a remarkable growth in the last decades, mainly motivated by the low fabrication costs provided by their CMOS compatibility, and the high-density integration enabled by their high dielectric contrast [1]
Once the feasibility of ZB operation in our design was demonstrated through homogeneous medium approximation, accurate simulations of the real sub-wavelength grating (SWG) structure (Fig. 1(a)) were carried out using 3D Finite Difference in Time Domain (FDTD) with a commercial photonic design software [31]
It is clear that an increment in the height of the waveguide core reduces the ZB tilt angle while increasing the resulting refractive index. This tendency in the tilt angle is consistent with the fact that waveguides with aspect ratios closer to 1:1 are inherently less birrefringent [13], and a lesser correction through SWG tilting is required, at the cost of increased leakage losses
Summary
Silicon-on-insulator (SOI) photonic platforms have experienced a remarkable growth in the last decades, mainly motivated by the low fabrication costs provided by their CMOS compatibility, and the high-density integration enabled by their high dielectric contrast [1]. A common approach to avoid birefringence-related issues at chip level is to separately process TE and TM modes through polarization diversity schemes [6], but this alternative requires efficient polarization beamsplitters [7], [8] and significantly increases system size and complexity [9] These disadvantages could be prevented by providing polarization-independent integrated photonic components, and waveguides with negligible birefringence. Stress engineering was proposed in order to correct the birefringence fluctuations with the waveguide core dimensions and the residual birefringence due to fabrication errors, providing slight control through the difference in the expansion coefficients of the materials [16] Different versions of this approach include modifying the thickness of the cladding layer [15], the shape of the cross section of the core [17] or integrating a piezoelectric film that allows an electric dynamic control of the birefringence [18], but all of them provide limited effectiveness in strip waveguides. The proposed topology provides a broad spectral response and improved robustness against fabrication deviations from the nominal design
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