Yield enhancement flow for analog and full custom designs reliability-rules automatic application

Abstract

As the variations of shrunk processes increase at rapid rate, the performance of fabricated analog and full custom chips remarkably fluctuate. This paper describes an effective automatic flow for reliability rules automatic application onto analog and full-custom ASIC designs, without introducing any new design rules check (DRC) violations in input design. This Yield enhancement flow has shown good improvements on used test designs, and ran in reasonable time. Based on the standardization methodology used, additional foundry Yield-enhancement-related recommendations can be also developed as extension to this flow seamlessly providing easy and quick new technology adoption and short Turnaround Time (TAT).