Yield degradation of integrated circuits due to spot defects

Abstract

Economy of integrated circuit fabrication in the presence of quasi-randomly distributed spot defects is described. The distribution of the defects is represented in terms of density and modeled as follows : 1) they are randomly distributed within a limited area; 2) the density in a wafer changes concentrically; and 3) the density is normally distributed from wafer to wafer with uniform deviation throughout a wafer. The yield degradation phenomenon due to such defects has been analyzed using a computer simulation technique. The effect of density variations in a wafer and between wafers has been mainly investigated. An extensive numerical study leads to the following conclusions. 1) The deviation of the yield versus chip-area relation from the simple exponential law is influenced more greatly by the nonuniform defect distribution in a wafer than by the density variation between wafers. 2) The increase of average yield due to the density variation between wafers is sometimes offset by the decrease of the accuracy in yield prediction. Process stabilization is essential for the economical production of a few large-scale chips.