Xtorus: An Extended Torus Topology for On-Chip Massive Data Communication

Abstract

In the context of more massive data to be processed and more processing elements (PEs) to be laid on a single chip or board, the requirements for corresponding interconnection network are becoming even higher. This paper presents a new topology called xtorus, and evaluates it by using both theoretical analysis and experimental simulation method. For theoretical analysis, an algorithm for computing link path diversity and link entropy is given. The analysis shows that, compared with mesh, xmesh, and torus, the proposed topology has better properties in terms of diameter, average latency, throughput, and path diversity. Although some more links are added in xtorus, the number of links is of the same order of magnitude with that of mesh, xmesh, and torus. It also takes advantage of increasing higher levels of VLSI process. Simulations on GEM5 show that xtorus has better scalability, and its average latency is less than that of mesh, xmesh, and torus by significant proportions respectively, especially when larger number of routers are used. Moreover, to different traffic patterns, its performance swing is less than that of mesh. Finally, based on the entropy difference of the links in the topology, a method for heterogeneous link design is presented, which enables designers to trade off between delay, power and area according to concrete integrated circuit design scene.