X-architecture zero-skew clock tree construction with performance and DFM considerations

Abstract

As IC fabrication technologies get into nanometer era, clock routing gradually dominates SOC performance indicated by delay, cost, and power consumption. Moreover, the yield losses of clock tree induced by antenna effect and via failures are the critical problems in DFM. Based on X-architecture routing patterns, we propose a system of X-architecture zero-skew clock tree construction with performance and DFM considerations. The system first constructs an X-clock tree and inserts buffers for reducing delay. To fix the antenna violations in clock tree, jumper insertion and layer assignment techniques are applied. Moreover, redundant vias are placed to improve via yield. Experimental results on benchmarks show that our system can outperform the existing works on delay reduction, power saving, via count, antenna violation fixing, and double-via insertion rate.