Wu, Chung-Yu and Cheng, Kuo-Hsing: ‘Latched CMOS differential logic (LCDL) for complex high-speed VLSI’ IEEE J. Solid-State Circuits Vol 26 No 9 (September 1991) pp 1324–1328

Abstract

A group of high-speed, low-power, monolithic thin-film diode-transistor logic (DTL) circuits is described for computer and counter applications. Two major areas of technological advance in digital integrated circuits are: (a) increasing speed for a given power dissipation product and (b) decreasing area per gate function leading to the development of more complex single-chip units. The DTL circuits and subsystems described develop these trends to faster and more complex DTL single-chip logic functions. A basic die rather than a master wafer approach was taken, since most circuits in the DTL system can be fabricated in terms of the basic single NAND gate.Propagation delay times of 4·5 nsec for the basic NAND gate have been achieved, with a typical average of 5·7 nsec, at a power level of 11·7 mW (F.O. = 5). This allows a binary counting capability up to 40 mc. Average set and reset times on RS flip-flops are typically 16 and 18 nsec respectively. The basic die pattern is such that a single NAND gate, dual NAND gate, RS flip-flop, fan-in expander can be made from a single die pattern by simple changes in the final interconnection mask. Similarly, an exclusive OR, impedance buffer, or one-shot multivibrator, can be made with two adjacent basic dice. The basic die topology described is well suited to the formation of monolithic single-chip DTL binary elements, full adders, multibit counters and shift registers. Methods of measurement and dynamic response data are also presented.