Abstract
Energy is a scarce resource in real-time embedded systems due to the fact that most of them run on batteries. Hence, the designers should ensure that the energy constraints are satisfied in addition to the deadline constraints. This necessitates the consideration of the impact of the interference due to shared, low-level hardware resources such as the cache on the worst-case energy consumption of the tasks. Toward this aim, this article proposes a fine-grained approach to analyze the bank-level interference (bank conflict and bus access interference) on real-time multicore systems, which can reasonably estimate runtime interferences in shared cache and yield tighter worst-case energy consumption. In addition, we develop a bank-to-core mapping algorithm for reducing bank-level interference and improving the worst-case energy consumption. The experimental results demonstrate that our approach can improve the tightness of worst-case energy consumption by 14.25% on average compared to upper-bound delay approach. The bank-to-core mapping provides significant benefits in worst-case energy consumption reduction with 7.23%.
Highlights
Real-time embedded systems are becoming widespread, ranging from sensor networks, Internet of Things (IoT) systems,[1,2] and surveillance systems to satellite subsystems
The bank-to-core mapping is given in advance, and we show the impact of the bank-level interference on worst-case energy consumption (WCEC)
To quantify the impact of interference on WCEC, we assume the bankto-core mapping is given as shown in Table 2, and the deadline of HRTi is equal to its period; we compute the WCEC of each task considering interference delay and not-considering interference delay, respectively, and compare the difference between them
Summary
Real-time embedded systems are becoming widespread, ranging from sensor networks, Internet of Things (IoT) systems,[1,2] and surveillance systems to satellite subsystems. For real-time embedded systems, energy consumption are important design issues, since most of them operate on batteries or drain energy from limited sources. Besides bounding worstcase execution time (WCET) of a task, designers need to analyze the worst-case energy consumption (WCEC) of the task for avoiding potential system failures due to inadequate energy supply at runtime. Real-time systems are increasingly moving toward multicore architectures. To mitigate the high latency of the off-chip memory, multicore architectures are usually equipped with the on-chip caches.
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