Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors

Abstract

Next-generation, multi-core Internet of Things (IoT) processors use advanced technology nodes that have increased reliability issues such as Negative Bias Temperature Instability (NBTI). Run-time feedback reliability mechanisms used on current multi-core processors incur too much area and power overhead leading to limited design space for IoT applications. In the typical ASIC design flow, switching activity files are used in order to model the reliability-driven performance loss. However, for multi-core ASIC design, the typical switching activity files lack multi-threaded software workload information thus lacking representation of modern workloads. The exact switching activity for a multi-core design can be established using a logic simulator, which captures the scheduling and execution order of multi-threaded workloads but suffer from long run times when dealing with real workloads. This paper proposes a method to obtain multi-threaded switching activity signatures in a short period of time using a performance (gem5) and a logic simulator (VCS) for IoT applications. These switching activity files are compiled into a workload signature and through this work, maintain compatibility with design tools. This workload signature is used in the standard ASIC design flow for lifetime improvement by mitigating the reliability issues such as NBTI at design-time. Experiments are performed using real workloads on an OpenSPARC T1 core. The default-sized T1 core is improved to have a reliability increase of 4.1×, leading to a desired reliability time of 10 years.