Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting

Abstract

The recent advances in thin-film thermoelectric (TE) materials have created opportunities for on-chip cooling and energy-harvesting with heat-fluxes >100W/cm2. However, it remains unclear how effective these materials are in the context of realistic microprocessor floorplan and workloads. Moreover, these TE materials suffer from contact parasitics that can significantly impact their performance. To evaluate the workload dependent performance of on-chip TE devices, we developed a hierarchical simulation methodology that connects an architectural simulator and a power estimation tool with a thermal simulator capable of simulating TE devices. The well-known HotSpot thermal simulator is modified to incorporate TE equations along with contact parasitics in the TE module. SimpleScalar and McPAT were used to generate the runtime power of different functional units in an Out-of-Order processor across the SPEC2000 workloads. The power-map generated by McPAT is used by our TE enhanced HotSpot simulator to evaluate the cooling and harvesting capabilities of on-chip TE modules. Our results indicate that it is possible to obtain 11°C peak cooling at the hot-spots, or harvest upto 85mW of power from the hot-spots. We also show that on-chip TE devices can aid in boosting the clock frequency of the processor from 1200MHz to 1600MHz under iso-temperature comparison with the no-TE case. This framework also allows for the rapid design space exploration of TE module's material/physical parameters and the optimum placement options for the TE module on the chip floorplan.