Abstract
Researchers have demonstrated the benefits of hardware worklist accelerators, which offload scheduling and load balancing operations in parallel graph applications. However, many of these applications are still heavily memory latency-bound due to the irregular nature of graph data structure access patterns. We utilize the fact that the accelerator has knowledge of upcoming work items to accurately issue prefetch requests, a technique we call worklist-directed prefetching . A credit-based system to improve prefetch timeliness and prevent cache thrashing is proposed. The proposed prefetching scheme is simulated on a 64-core CMP with a hardware worklist accelerator on several graph algorithms and inputs. Enabling worklist-directed prefetching into the L2 cache results in an average speedup of 1.99, and up to 2.35 on Breadth-First Search.
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