Abstract

Abstract This paper presents a power efficient realization of block least mean square (BLMS) algorithm based adaptive finite impulse response filter (ADF) using offset binary coding (OBC). OBC method is one of the area optimization methods of distributed arithmetic (DA). In the DA scheme partial products of the filter are stored in a look-up table (LUT) followed by a shift accumulate unit (SA). The size of the LUT increases exponentially with length of the filter. Using the OBC method, the size of the LUT is reduced. Memory sharing concept is used to design the registers, which are in turn used for input sample generation. A high range of parallelism is included in the architecture that enhances its performance. The adaption delay is decreased by doing parallel LUT update, filtering and weight updation operations. The results prove that the proposed design consumes 42% less power in comparison to the best existing architectural designs.

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