WITHDRAWN: High performance IIR filter design with MOD-GDI based array multiplier

Abstract

Abstract Due to an upsurge in technology, there is a need for development resemblance in portable devices besides its high speed and low power capability. The most critical factors are area, total power dissipation, and propagation delay to estimate a device's performance. Signal processing modules viz. Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters are fundamental elementary logics in DSP systems. Performance optimization of a digital IIR filter is always trendy for VLSI DESIGN Engineers. We can also achieve by improving sub-modules' efficiency (like. adder, multiplier, and delay elements) required to realize the filter architecture. This paper aims to extract a layout of the IIR filter implemented using a high-speed 4-bit Array Multiplier. The multiplier for this IIR designed with Modified Gate Diffusion Input (MOD-GDI) technique reduces the additional circuitry, which reduces the area and average power dissipation of overall filter logic. Extracted the layout by using Mentor Graphics EDA tools (with 130 nm technology). Compared to the performance characteristics like area, delay, the power consumption of the proposed and conventional IIR filters. The proposed IIR filter is space-efficient and consumes less power than the traditional IIR filters.