Abstract
Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital processing applications. Sigma delta analog to digital converter architecture being digital dominant architecture is much suitable for signal processing applications. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture suitable for signal processing applications with a very few passive components connected externally to FPGA. Schematic level architecture of high-speed comparator working at a differential swing which is not allowed by standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed for On-chip Continuous-time Sigma-delta ADC architecture. Simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using H-Spice and Questasim simulations.
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