Wiresizing with buffer placement and sizing for power-delay tradeoffs

Abstract

With the increasing influence of the resistive effects of interconnects on the performance of VLSI systems, a greater stress is being laid on careful interconnect design. One prominent technique is the approach of sizing wires for long interconnects to achieve the desired speed and power characteristics. It has also been suggested that one may appropriately insert repeaters for significant delay reductions. This paper unifies these approaches to optimizing an interconnect by placing a prespecified number of buffers (drivers and repeaters) using a dynamic programming procedure and then performing simultaneous wire and buffer sizing using a sensitivity-based heuristic. Experimental results are presented to prove the utility and performance of the approach.