Abstract
Capacitive and inductive coupling I/Os are emerging non-contact parallel links for chips that are stacked in a package. The capacitive coupling utilizes a pair of electrodes that are formed by top layer of IC interconnections. The inductive coupling uses coils, just like a transformer, that are rolled by the IC interconnections. They are implemented by digital circuits in a standard CMOS. No new wafer process or mechanical process is required, and hence inexpensive. Since there is no pad exposed for contact, ESD protection structure can be removed. Chips under difference supply voltages can be directly connected, since they provide with an AC-coupling interface. This paper presents fundamental differences between the inductive coupling and the capacitive coupling. Secondly, advantages of the inductive coupling over Through-Silicon-Vias and micro-bumps are discussed. Circuit techniques to raise aggregated data rate to 1 Th/s, and lower energy dissipation to 0.14 pJ/h are presented. Future challenges and opportunities such as a 3D scaling scenario are described.
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