Abstract
The design and measurement of a wideband successive detection logarithmic amplifier (SDLA) monolithic microwave integrated circuit (MMIC) using InP double heterojunction bipolar transistor technology (DHBT), is described in this paper. The MMIC uses cascaded differential amplifier gain stages together with full wave detectors to achieve a piecewise linear approximation to the ideal logarithmic response. The configuration also includes a limited RF output and on chip adjustment for gain and detector slope. The integrated circuit provides 33 dB dynamic range across 2-18 GHz for a ±1 dB log error, with a limited RF output of >-2.2 dBm. The circuit consumes 690 mW from a single -5 V supply rail in a chip area of 2.58 mm2. (6 pages)
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