Abstract

In this paper, we propose a new wide-scan active directintegrated 1×5 phased array antenna (AIPAA) for mm-Wave applications. The AIPAA’s unit-cell comprises three K-band miniaturized tapered slot elements, a GaN high electron mobility transistor (HEMT) as a power amplifier (PA), a stability circuit, an input matching network, and biasing components. The tapered slot antenna element is reshaped so that its input impedance closely matches the optimal load impedance of the HEMT (Z <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>opt</i></sub> =6+j38Ω at 22 GHz), which enhances the system efficiency. The peak integrated PAs’ Power-Added Efficiency (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>p</i></sub> ) is ≥ 56% with ≤ 9% variation over scan coverage (±50°) at 1.5dB power backoff from P1dB. The peak AIPAA system Power-Added Efficiency (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>s</i></sub> ) is 51% with a peak array radiation efficiency of 92%. The relative frequency bandwidth with PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>p</i></sub> above 25% is between 9%-13% over the scan range. The proposed AIPAA demonstrates less than 0.9dB and 1dB scanloss over the scan coverage in terms of antenna array gain and PAs’ power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>p</i></sub> ), respectively. The peak PA-integrated array gain and EIRP at P1dB of 24dBi and 51dBm are achieved, respectively. The proposed AIPAA’s size is 18 × 58 × 17mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> with a cell of 9.2 × 6.5 × 1.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . The measurements are in good agreement with electromagnetic and circuit co-simulation results.

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