Abstract
A fully depleted silicon-on-insulator (FD SOI) device having an ultrathin buried oxide (BOX) with a 45-nm fully silicided (FUSI) NiSi gate, and a hybrid SOI/bulk complementary metal oxide semiconductor (CMOS) integration process have been developed. The optimal threshold voltage (Vth) for low stand-by power (LSTP) applications in FUSI gate silicon on thin BOX (SOTB) MOSFETs was achieved while keeping a lightly doped channel. By using back-gate bias, we have demonstrated the optimization of device power and performance and a reduction in Vth variation after device fabrication. We have also shown that the characteristics of the integrated hybrid bulk transistor are comparable to those of conventional bulk transistors.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
