Wide range-low jitter PLL design for serializer

Abstract

The paper presents the wide range phase-locked loop design for serializer. Serializer converts the 16 bit parallel data into serial, thus 16 times fast clock is required to synchronize the parallel data and serial data. PLL generates 16× serial clock from the parallel clock by frequency multiplication. PLL is simulated with 0.18 µm CMOS process. Major challenge of PLL design is to achieve large dynamic range. The PLL design for large dynamic range suffers from a high jitter at lower frequency and linearity issues. Advance CSVCO has been simulated with source degeneration technique and achieve wide linear range from 14 MHz to 1.05 GHz with 99.2 % linearity. The PVT Corners simulation shows 16 MHz to 1.04 GHz output range. Average power dissipation of the proposed PLL design is 2.7 mW. Worst case Peak to peak period jitter is 13.4 ps and rms jitter is 2.6 ps for 800 MHz output frequency.