WIB-SAR: Write Intensity Based Selective Address Remapping

Abstract

The transistor density within chips has increased dramatically in recent years. This leads to the development of many core systems which allows more than one application to run concurrently resulting in a high pressure on the memory subsystems. Researchers are trying to find new alternatives to traditional DRAM based memories because of their inherent limitations like low density and high leakage power. Emerging Non-Volatile memories such as Phase Change Memory (PCM) and Resistive RAM can be considered the most promising candidates for main memories due to many useful properties, such as non-volatility, high density, and low leakage power. However, drawbacks such as limited write endurance and high write energy reduce the chances of replacing traditional DRAM with non-volatile memory. In this paper, we propose a write variation-aware selective address remapping (WIB-SAR) scheme to improve the lifetime of PCM memories. The proposed scheme judiciously monitors the write accesses to different locations within the memory. Through this monitoring, WIB-SAR remaps heavily written addresses with less written addresses within a segment to evenly distribute the writes. Our method tries to improve the lifetime with minimum energy overhead. Experimental results show that the proposed technique improves lifetime by 168% with a minimum energy overhead of 1.1% over existing techniques.