Whitespace-aware TSV arrangement in 3D clock tree synthesis

Abstract

Through-silicon via (TSV) could provide vertical connections between different dies in three-dimensional integrated circuits (3D ICs), but the significant silicon area occupied by TSVs may bring great challenge to designers in 3D clock tree synthesis (CTS) because only few whitespace blocks can be used for clock TSVs after floorplan and placement. Unlike most of the published previous works that ignore whitespace, this paper for the first time proposes a whitespace-aware TSV arrangement algorithm in 3D CTS. The algorithm consists of three stages: sink pre-clustering, whitespace-aware three-dimensional method of means and medians (3D-MMM) topology generation and deferred-merge embedding (DME) merging segment reconstruction. We also present a TSV whitespace-aware 3D CTS flow. Experiment results show that our proposed algorithm is more practical and efficient, the average skew and power can be reduced by 49.2% and 1.9% respectively, compared to the traditional 3D-MMM based CTS method with TSV moving adjustment.