Abstract

With the upcoming era of Internet of Things and the Pervasive Computing, there is a need to develop block ciphers with tight constraints such as area, power, memory, performance, throughput and others. These are so called the lightweight block ciphers which are specifically intended for resource constrained platforms. Lined up in the line is SIMON, a light weight block cipher proposed by NSA after the prompting from the U.S. Government in the year 2013 along with SPECK lightweight block cipher. SIMON implementation on hardware has excellent results in terms of area and has been found to be a very strong alternative to the existing AES. This paper involves the basic design considerations, round functions, key schedule and parameters of SIMON and also we can look forward into the implementations of SIMON in hardware comparing with the existing AES standard. This paper also focuses on the analysis in terms of area, power and delay of the SIMON 64/128 configuration in Cadence Synthesis RTL Compiler using the CMOS 180 nm and 90 nm technology libraries.

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