Wet-Etched Three-Level Silicon Interposer for 3-D Embedding and Connecting of Optoelectronic Dies and CMOS ICs

Abstract

Ultracompact optical submodules for parallel optical interconnects are demonstrated based on a three-level silicon interposer, which is fabricated through a low-cost wet etching process. Using three steps of wet etching of silicon, a multilevel cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through-silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50-μm thermal isolation air gap is formed between dies as a part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness. Based on this 3-D packaging concept, compact 4 mm × 6 mm, 10-Gb/s 12-channel transmitter and receiver submodules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 and 15 Gb/s for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver submodules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . Also, crosstalk for both modules is tested, yielding only a 0.1and 0.8-dB additional penalty for transmitter and receiver, respectively.