Wear-Leveling Techniques for Nonvolatile Memories

Abstract

Nonvolatile memories (NVMs) are promising technologies for replacing SRAM or eDRAM in low-level on-chip caches and main memories because they can save standby power and provide high cache capacity. However, limited write endurance is a common problem for NVM technologies. The current memory management policies are not write variation aware and result in significant nonuniformity in terms of writing to memory blocks, which would cause heavily written nonvolatile cache blocks to fail much earlier than most other blocks. Thus, wear-leveling techniques are important for NVM-based memory system to balance write traffic and extend the system lifetime. Some wear-leveling techniques have been proposed for NVM-based main memories and on-chip caches. In this chapter, we use inter-/intra set write variation aware cache policy (\({\text {i}}^{2}{\text {WAP}}\)) as an example to show how to design an endurance-aware management policy for nonvolatile caches. \({\text {i}}^{2}{\text {WAP}}\) has two features: first, Swap-Shift (SwS), an enhancement based on previous main memory wear leveling to reduce cache inter-set write variations; second, probabilistic set line flush (PoLF), a novel technique to reduce cache intra-set write variations. Implementing \({\text {i}}^{2}{\text {WAP}}\) only needs two global counters and two global registers. By adopting \({\text {i}}^{2}{\text {WAP}}\), we can improve the lifetime of on-chip nonvolatile caches by 75 % on average and up to 224 %.