Wear-out of ultra-thin gate oxides during high-field electron tunnelling

Abstract

Ultra-thin (<6 nm) SiO2 wear-out is characterized by time-dependent dielectric breakdown and stress-induced leakage current (SILC) measurements on n+ poly-Si/SiO2/n-Si capacitors, stressed by high-field tunnel injection of electrons from the Si substrate. A drastic increase of the charge to breakdown (QBD) and a strong decrease of the SILC are observed for thinner oxide layers and lower tunnel current densities. This is explained by the corresponding reduction of the hot-electron energy during stressing. With the decrease in gate oxide thickness from 6 nm to 3 nm, a transition from Fowler-Nordheim to direct electron tunnelling is observed in the current-voltage characteristics of the capacitors. It is demonstrated that no significant wear-out occurs in a 3.5 nm oxide layer for direct tunnelling of electrons from the Si substrate.