Abstract
In this paper, an electro-thermo-mechanical finite-element method (FEM) simulation approach is proposed to analyse the wear-out evolution of multiple-bond-wires chips in power electronic modules. Cracks are introduced along the simulation, based on the sensitive damage position at each simulation step, in order to emulate the realistic wear-out sequence occurring in real cases. This process has been made semi-automatically, by running many simulations, each time with updated crack geometry using the previous step results. The proposed method has been successfully used to interpret the typical on-state voltage degradation curve of accelerated life tests.
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