Abstract
The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In0.5Ga0.5As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm2 at −1 V and a responsivity up to 0.2 A/W at −2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results.
Highlights
The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links
As the amount of data generated from modern communication applications such as cloud computing, analytics, and storage systems is increasing rapidly, silicon electronic integrated circuits (ICs) are suffering from a bottleneck at the interconnection level resulting from the resistive interconnect[1,2]
In the past few years, research efforts have been focused on the development of scaled hybrid III-V/ Si nanophotonic devices, including nanowire photodetectors[13,14], nanowire light sources[15,16,17], and photoconductors acting as both detectors and emitters coupled by a polymer waveguide[18]
Summary
The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. High-performance on-chip detectors and lasers have been demonstrated based on bonding of a III-V laser stack including quantum wells on top of a silicon wafer with pre-fabricated waveguides and passives[8,9,10]. High crystal quality III–V nanowires can be achieved and used for devices, the vertical geometry from a device fabrication perspective requires additional engineering and pick-andplace methods for on-chip integration and waveguide coupled solutions[19,20]. These limitations may be overcome with templateassisted selective epitaxy (TASE)[21,22,23]
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