Waveform approximation technique for CMOS gates in the switch‐level timing simulator BTS

Abstract

A switch‐level timing simulator has the advantage of fast speed and good adaptability for VLSI circuits, but it cannot offer accurate transient waveform information. In this paper an accurate and efficient switch‐level timing simulator is described. The high accuracy is attributed to a new waveform approximation technique, which includes delay estimation and slope estimation. Efficient delay and slope calculations are accomplished through a switch‐level simulation instead of using a transistor‐level simulation. A new approach for delay estimation is presented which models the delay behavior of an RC tree by two equations: a dominant delay equation and an error delay equation. Both are derived by surface fitting to approximate the surface that is measured from the actual delay behavior of a CMOS gate. A modified approach for slope estimation is also investigated which has close relationship with the equivalent RC time constant of the evaluated cluster circuit. This equivalent RC time constant can be obtained by traversing the tree recursively. The results show good agreement with SPICE.