Abstract
Wave pipelining is a technique which can be used to speed up the circuit without insertion of storage elements, but because of that fact, needs to be more tightly controlled when being designed. This paper - taking the wave pipeline design constraints into account - looks to automate the generation of wave pipelined design netlists through synthesis and delay balancing scripts. The results show less than 20% delay deviation between maximum and minimum delays which was the target criteria and is comparable to numbers from hand-crafted designs
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