WASA: a low power front-end ASIC for time projection chambers in 65 nm CMOS

Abstract

A low power front-end ASIC, named WASA has been developed for the time projection chamber for the CEPC (Circular Electron Positron Collider) experiment. Power consumption becomes very critical and is addressed by using 65 nm CMOS process and circuit structure with simple analog circuits. Three prototype ASIC chips have been designed and fabricated, including the 5-channel analog front-end (AFE) chip, the SAR ADC chip and the mixed-signal chip with the AFE and the ADC together. Only the design and the test results of the AFE and the SAR ADC chips are reported in this paper. The power consumptions of the AFE and the SAR ADC core were measured to be 2.0 mW and 1.0 mW per channel respectively. The gain and the ENC noise of the AFE were 8.91 mV/fC and 644 electrons @ 10 pF input capacitance, including the contribution of 460 electrons from the external buffer for test purpose. The INL was less than 0.5% for a dynamic range of 145 fC. The maximum crosstalk between two adjacent channels was 0.39%. The SNDR and SFDR of ADC were measured to be 57.2 dB and 79.4 dBc at 50 MS/s for a 2.4 MHz input sine signal, corresponding to an ENOB of {9.2} bit. The total ionizing dose (TID) tests were also done for the AFE and the SAR ADC. No significant performance degradation {was} observed for the total dose up to 1 Mrad (Si).