Warpage Simulation and Optimization of Fan-Out Wafer level Package(FO-WLP) with TMV under Different Processes

Abstract

Fan-Out wafer-level package (FO-WLP) has become a mainstream advanced packaging technology and from the first generation fan-out package, the second generation of new fan-out packaging technologies, such as FO MCP, FO POP, and POP SiP is gradually derived. In FO-WLP, wafer warpage caused by mismatch of coefficients of thermal expansion (CTE) between materials has always been an important matter. This paper aims at a FO POP package, which uses through mold via (TMV) to achieve the upper and lower interconnections between packages. The packaging method is chip-first and face-up. The wafer warpage in each thermal process of the package is simulated and analyzed. At the same time, the chip spacing, molding compound thickness, TMV diameter, carrier thickness and material effect on warpage in the plastic molding process and copper layer thickness, copper area ration, dielectric layer thickness and material effect on warpage in the re-distribution layer (RDL) process is studied. And an effective method for reducing wafer warpage in each thermal process is proposed.