Wakeup synthesis and its buffered tree construction for power gating circuit designs

Abstract

A power gating circuit suffers from large amount of rush current when it wakes up, especially when all switch cells are turned on at the same time. If each switch cell is turned on in different instant of time, the rush current can be reduced. It is shown in this paper that the rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. The wakeup synthesis that we define is to determine the turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while rush current is kept below the maximum value that is allowed. The corresponding synthesis algorithm is proposed. The determined turn-on time and signal slew are implemented using a buffered tree, where a source is a wakeup signal and sinks are multiple switch cells; the synthesis algorithm to generate the tree is proposed. The wakeup synthesis and buffered tree construction are integrated into a design flow that receives a netlist of power gating circuit as an input and produces a layout of netlist with wakeup network embedded. Experiments in an industrial 1.1 V, 45-nm technology demonstrate that the wakeup delay is reduced by 43% on average of example circuits compared with 2-pass turn-on, which is widely used.