Wafer-scale Fabrication of Vertical GaN p-n Diodes with Graded JTE Structures Using Multiple-zone Boron Implantation

Abstract

In this study, a novel graded junction termination extension (JTE) structure is proposed for high voltage vertical GaN power devices. A multiple-zone boron implantation layout used to form a graded acceptor concentration profile along the JTE enables us to obtain p-n diodes with high avalanche immunity over 1200 V. In wafer- scale fabrication of the p-n diodes on a 4-inch free-standing GaN substrate, good reverse characteristics are observed across the wafer, showing breakdown voltage distribution of as much as 1450 V with circular symmetry. We demonstrate double-pulse switching waveforms at 400 V for the p-n diodes and show reverse recovery properties that reflect a short carrier lifetime specific to GaN. The proposed JTE technique has high potential for wafer-scale fabrication of robust and highly efficient vertical GaN devices.