Abstract
Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25- $\mu \text{m}$ -thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold–aluminum (Au–Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 $\mu \text{m}$ , respectively. Despite the small sealing footprint, the Si caps with 9- $\mu \text{m}$ -wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than ${2.8}\times {10}^{-14}$ mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 $\mu \text{m}$ by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip–chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages. [2018-0257]
Highlights
V ACUUM packaging is a process for encapsulating a device (e.g. a micro-electromechanical systems (MEMS) or nano-electro-mechanical system (NEMS) device) in a vacuum environment and maintaining the internal vacuum level using hermetic seals
For the small Si caps, the theoretical cap deflection is on the order of a few nanometers (calculated according to equation (1) in section III.C), which is below the detection limit of our measurement setup, the sealing yield of small cavities cannot be confirmed by this method
The protrusion of the transferred Si caps out of the cavity wafer plane were within 31 ± 1 μm, which is below typical solder and stud bump heights of ∼50 μm after flip chip bonding [47]
Summary
V ACUUM packaging is a process for encapsulating a device (e.g. a MEMS or nano-electro-mechanical system (NEMS) device) in a vacuum environment and maintaining the internal vacuum level using hermetic seals. In the case of sacrificial and sealing films made of silicon oxide, silicon nitride, or poly-silicon, the deposition processes typically involve high temperatures, which may hinder its use for many applications, e.g. sealing of MEMS on ICs. In contrast, hermetic sealing of devices by bonding caps on top of the devices is a more versatile approach. The use of thin single crystalline Si caps in combination with narrow metal sealing rings (< 10 μm) aims to provide a reliable and space-efficient solution for fully hermetic packaging of MEMS and NEMS, and potentially for high-density 3D integration with ICs. the hermeticity of the sealed cavities and the strength of the bonds are evaluated. The influence of sealing ring width on the resulting sealing yield and the possibility of encapsulating cavities of various dimensions using the thin Si caps are investigated
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