Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

Abstract

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.