Abstract

This discussion group explored areas in wafer level reliability testing that seem to cause the greatest confusion in the when attempting to relate wafer level tests to expected field failure characteristics. Many people would like to go well beyond the basically monitoring only function of the wafer level reliability tests and extrapolate the wafer level test results to at use conditions. In general the complexity of the interaction of the secondary failure mechanisms stimulated by the highly accelerated wafer level tests precludes any extrapolation to at use conditions. In an attempt to clarify the limitations imposed by wafer level reliability testing we explored the issues related to interpreting wafer level reliability test data. In addition there were some attendees that wanted to pursue the issue of what modelling research is needed to address the desire extrapolation to at use conditions. The first issue raised has been discussed many times before: It is critical to have more failure analysis of field returns in order to accurately correlate information gathered at the wafer level with field experience. In many cases there is very little information about the degree to which the design style used by the circuit designer relates to the predictability of a device based upon only information on the physics of failure gathered from wafer level tests. If the CAD tools do not set clear limits on what designers can do to avoid reliability hazards there is a significant possibility that there will be little of no correlation between field failure experience and wafer level test results. No amount of physical model accuracy which takes into account the high stress levels at wafer level can allow correlation with field failures when design stress constraints are violated intentionally or accidently. Another issue raised was related to the fact that there is a much greater probability of a field failure that resulted from a small point defect than there is for a field failure that is caused by a basic materials fault. This is because the wafer level reliability test structures as defined are not intended to look for point defects, only tests for global materials quality changes. Typically the area of wafer level reliability test structures are small compared to the product devices and therefore can not detect low defect density. Based upon this, the real issue is defect distribution rather than wear-out. Related to the above is the observation that the global defects that are detectable by wafer level reliability testing are no less defects than point defects. The only difference is that they are detectable with small area test structures. It was noted that there are nondestructive methods for detecting these defect populations:

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