Wafer level processing of 3D system in package for RF and data application

Abstract

System integration is clearly a driving force of innovation in packaging. The need for miniaturization has led to new system in package architectures, which combine disparate technologies. When several dies have to be connected in a small package, stacking appears to be the best solution. However, this 3D packaging has to satisfy high interconnection density, high data throughput with good signal integrity, and reliability needs while keeping a low cost. New developments on wafer level packaging and 3D packaging are in progress in a European project called Walpack (PIDEA project n/spl deg/ 01-131). The aim of this project is to develop equipment and processes for smart card, RF communications and 3D system in package. This paper is mainly focused on two different 3D packaging approaches proposed respectively by 3D-PLUS and Thales: ultra-thin 3D module; stacking of multi chip module with integrated passives. The major interest is to base process packaging at wafer level. Both the first results on packaging concepts and the first electrical results are presented and commented in this paper.