Wafer level packaging and 3D interconnect for IC technology

Abstract

The important factors for packaging technology are IC packaging costs, the impact of the package on circuit and system performance, and the reliability of the package. Wafer level packaging technology is a promising solution for future IC generations. This paper reviews the wafer level bumping process and its requirement for thick resist coating and full field aligned exposure. 3D interconnect technology is a viable solution for increasing electronic device functional density and reducing total packaging costs. The critical issue is the ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate. For CMOS devices, this technology can be applied to chip-scale packaging and also to advanced 3D interconnect processes. In this paper, we describe a new approach to wafer-to-wafer alignment using alignment targets at the bond interface, i.e. face to face wafer alignment (SmartVieW/sup TM/) that relies on precision alignment positioning systems to register and align wafers with one micron or better precision.