Wafer level packages (WLPs) using B-stage non-conductive films (NCFs) for highly reliable 3D-TSV micro-bump interconnection

Abstract

Higher packaging density demands to populate more circuits or chips on smaller substrate areas. 3-D stacking technologies have been developed for smaller package size and higher electronic performances. Among 3-D packaging technologies, the through silicon via (TSV) technology that uses Cu pillar/Sn-Ag micro-bumps to vertically interconnect between chips is the most advanced state-of-art packaging method. However, conventional flux and underfill process for bonding using Cu pillar/Sn-Ag micro-bumps has problems such as process complexity, flux residues and voids trapping. In this study, non-conductive films (NCFs) have been introduced to simplify the bonding processes and avoid flux residues and voids trapping. In addition, wafer level packages (WLPs) introduced using NCFs for 3D-TSV micro-bump interconnection have been investigated. At first, wafer level NCFs lamination was conducted without voids and bubbles formation on a wafer. And the effect of liquid type epoxy on the adhesion and elongation properties of NCFs laminated on a wafer was also investigated to optimize the wafer dicing process using laminated NCFs. After NCF laminated Cu/Sn-Ag bumped wafer was diced into a single chip, singulated chips were bonded on substrate chips using a flip chip bonder. The electrical properties of WLP packages using NCFs were evaluated and compared with conventional single chip packages. As a result, WLPs using NCFs showed the same electrical interconnection properties with conventional single chip packages.