Wafer level integration of an advanced logic-memory system through 2nd generation CoWoS® technology

Abstract

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS®) has been applied for the first time in fabricating high performance wafer level system-in-package (WLSiP) containing the 2nd-generation high bandwidth memory (HBM2). An ultra-large Si interposer up to 1200 mm2 made by a two-mask stitching process is used to form the basis of the 2nd-generation CoWoS® (CoWoS®-2) to accommodate chips of logic and memory to achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approach such as chip-on-substrate first (CoS-1st), CoWoS® offers more competitive design rule to result in better power consumption, transmission loss, and eye diagram. CoWoS®-2 has positioned itself as a flexible 3D IC platform for logic-memory heterogeneous integration between logic SoC and HBM for various high performance computing applications.