Wafer-Level Fabricated Tight-Coupling Dual-Solenoid Transformer Chips With Watt-Scale Power Transfer

Abstract

Reported are a novel kind of tight-coupled dual-solenoid transformers (DSTs) which are on-chip integrated by using wafer-level fabrication including a low melting-point zinc-aluminum alloy rapid microcasting technique. Without magnetic core used, the silicon-chip integrated transformer is with the two metal solenoids tightly interwound to form a highly-coupled 3-D structure, thereby performing high inductance density and featuring no concern in magnetic flux saturation. Fabricated with the wafer-level thick-metal 3-D microcasting technique, the DST exhibits sufficient inductance value and low dc resistance while maintaining tiny footprint. Various DST structures are designed, fabricated and characterized for performance optimization. The optimally designed DST chip demonstrates a compact footprint of 2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a high inductance of 193.14 nH (i.e., inductance density = 96.57 nH/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and a small dc resistance of 1.09 Ω. The test shows that the chip achieves an ultrahigh coupling coefficient of 0.95 and superior maximum transformer efficiency of 87.8% at 100 MHz. More importantly, the DST achieves <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Watt</i> -scale power transfer capability at 100 MHz, where no any heat dissipation treatment to the chip is used. Therefore, the on-chip DSTs are very promising for power/signal transmission in various electronic microsystems.