Wafer level analysis and simulation of back end of line chemical mechanical polishing processes

Abstract

The Chemical Mechanical Polishing (CMP) variation on a die is a function of the die’s location on the wafer. For example, the post CMP thickness and/or topography variations in the center die can be very different from those in the mid-radius and edge dies. Consequently, the number of CMP hotspots and the hotspot locations can vary from die-to-die on a given wafer. Most commercial CMP simulation tools in the Design for Manufacturing (DFM) field focus on predicting CMP topography and thicknesses for a single die on the patterned wafer, and do not have wafer level prediction capabilities. For CMP simulation to be more effective in process and layout optimization, CMP simulation tools should be able to accurately predict CMP performance at the feature-scale, within the die, and across the entire wafer. In this paper, we analyze CMP data from multiple dies on back end of line (BEOL) Cu interconnect levels and show the wafer level effects in a polishing process. We use the data to calibrate Cadence’s integrated wafer level and die level CMP models and use the calibrated models to predict the CMP pattern dependencies on multiple dies across a product chip wafer. Finally, we show a comparison of the simulation to measured data.