Abstract
A wafer level integration method is proposed for building large capacity bubble memory chips using present processing technology. A single cell pattern is stepped and repeated to generate a matrix of cells. Each cell has basically a major-minor structure. With exchange switch pairs and geometry tolerant junction elements, the bubbles can be transferred between major loops of the adjacent cells in the same row or column. The control functions of those cells in the same row are also interconnected to the edge of the wafer, and thus can share the same driver electronics. These cells are integrated magnetically and electrically. They can share one or a few I/O ports and effectively form a large capacity chip. Since all the cells are identical, the final chip size can be any combination of the cells. A yield model study is performed to show the relationship between chip size and yield.
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