Abstract
W-CDMA 단말기에 적용 가능한 balanced 전력증폭기의 load insensitivity 특성을 분석하였다. Balanced 전력증폭기 내부에 있는 두 평형(parallel) 증폭기의 부하 임피던스가 출력 부하 임피던스의 부정합(load impedance mismatch)에 따라 어떻게 변화하는지를 수식적으로 계산하였고, 이를 통해 선형성이 가장 취약한 반사 계수 위상을 조사하였다. 이 위상에서 balanced 전력증폭기는 출력단의 트랜지스터 면적을 적절히 증가시킬 경우 선형성이 개선될 수 있음을 제안하였고, 트랜지스터 면적이 서로 다른 복수개의 1단 balanced 전력증폭기를 설계하여 VSWR=4:1 반사 조건에서의 시뮬레이션을 통해 이를 검증하였다. The load-insensitivity of the balanced power amplifier(PA) for W-CDMA handset applications is analyzed. The load impedances of the two parallel amplifiers in the balanced PA depending on the output load mismatch are mathematically calculated and with the result, the phase of reflection coefficient at which the linear output power is severely degraded is investigated. From the analysis, we proposed that the linearity of the balanced PA at the phase can be improved by properly increasing the transistor size and thus, multiple balanced PA's with different transistor size are designed and simulated. The simulation result showed that the balanced PA with larger transistor size has improved linear output power under VSWR=4:1.
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