Vulnerability study of hot solder dipped COTS components

Abstract

This paper details results from experimental tests and related finite element analysis aimed at understanding the stress levels which refinished leaded components could endure before showing signs of damage under solder dip loads. The experimental tests, termed “Dip-to-Destroy” (D2D), are formulated by altering solder dip processing parameters for solder bath temperature, dip time and preheat/no-preheat condition. The component types selected in the study represent constructional extremes for common classes of electronic parts. While the combination of higher solder temperature and longer dip time give increased risk of damage, as anticipated, the susceptibility to damage is also found to be strongly influenced by package design and construction. C-SAM examination is used to reveal delamination damage and the related finite element modelling results are used to undertake the comparative analysis. The metal heat path from the hot solder dipped terminations to the IC chip is clearly identified as the main factor for component vulnerability under defined hot solder dip loads.