Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints

Abstract

Advances in VLSI technology have made circuits more vulnerable to faults. Architectural vulnerability factor (AVF) reflects the possibility that a transient fault eventually causes an error in the circuit output. This factor represents the system vulnerability to transient faults and is used to compare different fault-tolerant designs or architectures. In this paper, we have introduced a simulation-based fault injection framework which is developed to evaluate the AVF of different adder hardware description models in various abstraction levels. Then, we introduce the most beneficial abstraction level for evaluating the vulnerability of a design. Finally, exploiting our fault injection framework, we compare the inherent fault tolerance of eight famous adders. We have explored the design space of different adder architectures while considering both delay and area constraints for comparing the inherent fault tolerance level of different adder architectures. To the best of our knowledge, this comparative study is not covered in the literature elsewhere.