Abstract
The silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has a more serious voltage overshoot than the silicon insulated gate bipolar transistor (IGBT) due to the fundamental differences of the devices’ parasitic parameters. In this paper, a novel low-inductance packaging structure for a wire-bond-based multichip phase-leg SiC MOSFET module to suppress the voltage overshoot is proposed. This packaging structure is based on the adjacent decoupling concept achieved by several decoupling capacitors to reduce the size of the commutation loop. The improvement in the packaging parasitics has been verified through an Ansys Q3D extractor. Furthermore, the influence of adjacent decoupling capacitors is analyzed in detail by frequency-domain analysis and verified with LTspice simulation analysis. Thereafter, the selection and thermal reliability of adjacent decoupling capacitors are expounded. The experimental results demonstrate the effectiveness and superiority of the proposed packaging structure.
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