Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits

Abstract

This paper illustrates a method to determine the optimal voltage, wire sizing and repeater insertion design rules for a global wire routing level that uses wave-pipelined interconnect circuits. In order to balance performance, power and area, a throughput-per-energy-area (TPEA) metric is introduced to guide the design of a global wire routing level to achieve maximum throughput (i.e. bit-rate) with optimal utilization of resources. A 180 nm technology case study for a memory bus channel that requires an aggregate throughput of 332.8 Gbit/s illustrates that the optimal TPEA combination of 1 V supply, 6 repeaters per centimeter, a metal thickness to width aspect ratio of 2.5 and metal pitch to width ratio of 3 gives 12 % reduction in dynamic power and over 60 % reduction in wire area as compared to a published interconnect circuit that uses low voltage differential signaling (LVDS).