Voltage scaling – a novel approach for crosstalk reduction in global VLSI interconnects

Abstract

PurposeTo analyze the effect of voltage scaling on crosstalk.Design/methodology/approachVoltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. VA (input at aggressor node A) and VB (input at victim node B) switching in same direction; VA is switching and VB at static low; VA and VB are switching in opposite direction; VA is switching and VB at static high.FindingsIt is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.Originality/valueVoltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.